The present invention relates generally to peak detectors and more particularly to a peak detector for a small input signal.
In optical disk applications, peak detectors are used. An AC peak detector is non-linear circuit used to obtain a steady state amplitude at a level of the peak amplitude of the input AC signal. The input AC signal need not be a uniform sinusoidal or an infinite sum of sinusoidals such as in a square wave signal, but any signal with approximately complimentary positive and negative voltage peaks, such as communication date signal, can be an AC signal.
A number of peak detector designs are known, however, each design has shortcomings which limit the range of operability and performance within that range. In particular, there is a need for peak detectors which detect peaks with amplitudes as low as 50 or even 20 millivolts. The known designs do not demonstrate acceptable performance at such levels and more particularly has dead zones where a new peak is not recorded.
FIG. 1 illustrates a prior art circuit where a new peak as an input signal is inputted to op-amp 100 as an input voltage. The op-amp 100 functions as voltage follower, and the op-amp 100 outputs a signal to transistor 102. Current flows through the collector to emitter of the transistor 102, when turned on by the op-amp 100. The transistor 102 conducts current through the collector to emitter and to capacitor 106. The capacitor 106 raises the gate voltage of PFET 108 and the corresponding source of PFET 108 to hold the new peak. The PFET 108 functions as source follower type buffering circuit. When the transistor 102 is off-state, a current source 104 discharges the capacitor 106.
FIG. 2 illustrates simulated waveforms including the input signals and the peak voltages in the prior art circuit. FIG. 2 includes two type input signals and the peak voltages. In FIG. 2, (a) is an input signal having 780 mV peak-to-peak amplitude, (b) is a peak hold voltage of the input signal (a), (c) is an input signal having 100 mV peak-to-peak amplitude, and (d) is a peak hold voltage of the input signal (c). The voltage of the signal (b) is about {fraction (91/100)}(percent) of the top peak voltage of the signal (a), and the voltage of the signal (d) is {fraction (68/100)}(percent) of the top peak voltage of the signal (c). The peak voltage, held by the circuit in FIG. 1, is lower than the peak of the input signal. The difference between the peak hold voltage and the actual peak depends on VBE of the transistor 102.
The present invention provides a peak detector that includes a differential comparator to compare the current peak with the new peak. The output of the differential comparator is used to control two current paths by two transistors, one current path controls a charging of a capacitor and the new peak voltage.